Prior to the use of a chip containing a memory array, each address in the array is tested to detect manufacturing defects that prevent the address from correctly storing information. Rather than discard a memory array chip that contains defects, considerable effort is expended to “repair” the defect(s) by logically replacing a defective row or column with another row or column that has been designated as a spare. Replacement logic ensures that references to the original row or column are routed to the replacement row or column.
The implementation of memory array repair typically requires extensive custom circuit design and introduces additional constraints on the main array. Additionally, the circuits to detect an access to a defective address and to multiplex the repaired memory elements into the array reduce the maximum operating frequency of the array. In most implementations, chip geography places further limitations on the repair elements, requiring that they be physically close to the defect.
A given repair element, or even a group of repair elements, can't repair every type of defect mechanism. For example, a cluster of failures in one physical area typically can't be repaired. Although necessary, the redundant array elements used for repairing defects, as well as their supporting circuits, can consume a significant fraction of the total array area and are frequently not used.